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<title>VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword Indices </title></head>
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<h1>VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword and Qword Indices</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/E n</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F38.W0 A2 /vsib</p>
<p>VSCATTERDPS vm32x {k1}, xmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed dword indices, scatter single-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F38.W0 A2 /vsib</p>
<p>VSCATTERDPS vm32y {k1}, ymm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed dword indices, scatter single-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F38.W0 A2 /vsib</p>
<p>VSCATTERDPS vm32z {k1}, zmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Using signed dword indices, scatter single-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.128.66.0F38.W1 A2 /vsib</p>
<p>VSCATTERDPD vm32x {k1}, xmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed dword indices, scatter double-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F38.W1 A2 /vsib</p>
<p>VSCATTERDPD vm32x {k1}, ymm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed dword indices, scatter double-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F38.W1 A2 /vsib</p>
<p>VSCATTERDPD vm32y {k1}, zmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Using signed dword indices, scatter double-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.128.66.0F38.W0 A3 /vsib</p>
<p>VSCATTERQPS vm64x {k1}, xmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed qword indices, scatter single-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F38.W0 A3 /vsib</p>
<p>VSCATTERQPS vm64y {k1}, xmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed qword indices, scatter single-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F38.W0 A3 /vsib</p>
<p>VSCATTERQPS vm64z {k1}, ymm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Using signed qword indices, scatter single-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.128.66.0F38.W1 A3 /vsib</p>
<p>VSCATTERQPD vm64x {k1}, xmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed qword indices, scatter double-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F38.W1 A3 /vsib</p>
<p>VSCATTERQPD vm64y {k1}, ymm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Using signed qword indices, scatter double-precision floating-point values to memory using writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F38.W1 A3 /vsib</p>
<p>VSCATTERQPD vm64z {k1}, zmm1</p></td>
<td>T1S</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Using signed qword indices, scatter double-precision floating-point values to memory using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>
<p>Op/En</p>
<p>T1S</p></td>
<td>
<p>Operand 1</p>
<p>BaseReg (R): VSIB:base,</p>
<p>VectorReg(R): VSIB:index</p></td>
<td>
<p>Operand 2</p>
<p>ModRM:reg (r)</p></td>
<td>
<p>Operand 3</p>
<p>NA</p></td>
<td>
<p>Operand 4</p>
<p>NA</p></td></tr></table>
<p><strong>Description</strong></p>
<p>Stores up to 16 elements (or 8 elements) in doubleword/quadword vector zmm1 to the memory locations pointed by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be stored if their corre-</p>
<p>sponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an excep-tion.</p>
<p>This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination register and the mask register (k1) are partially updated. If any traps or interrupts are pending from already scat-tered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction breakpoint is not re-triggered when the instruction is continued.</p>
<p>Note that:</p>
<p>Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if ModRM.rm is different than 100b.</p>
<p>This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.</p>
<p>The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are ignored.</p>
<p>The instruction will #UD fault if the k0 mask register is specified</p>
<p><strong>Operation</strong></p>
<p>BASE_ADDR stands for the memory operand base address (a GPR); may not exist</p>
<p>VINDEX stands for the memory operand vector of indices (a ZMM register)</p>
<p>SCALE stands for the memory operand scalar (1, 2, 4 or 8)</p>
<p>DISP is the optional 1, 2 or 4 byte displacement</p>
<p><strong>VSCATTERDPS (EVEX encoded versions)</strong></p>
<p>(KL, VL)= (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] (cid:197)</p>
<p>SRC[i+31:i]</p>
<p>k1[j] (cid:197) 0</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>k1[MAX_KL-1:KL] (cid:197) 0</p>
<p><strong>VSCATTERDPD (EVEX encoded versions)</strong></p>
<p>(KL, VL)= (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>k (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] (cid:197)</p>
<p>SRC[i+63:i]</p>
<p>k1[j] (cid:197) 0</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>k1[MAX_KL-1:KL] (cid:197) 0</p>
<p><strong>VSCATTERQPS (EVEX encoded versions)</strong></p>
<p>(KL, VL)= (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>k (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] (cid:197)</p>
<p>SRC[i+31:i]</p>
<p>k1[j] (cid:197) 0</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>k1[MAX_KL-1:KL] (cid:197) 0</p>
<p><strong>VSCATTERQPD (EVEX encoded versions)</strong></p>
<p>(KL, VL)= (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP] (cid:197)</p>
<p>SRC[i+63:i]</p>
<p>k1[j] (cid:197) 0</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>k1[MAX_KL-1:KL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VSCATTERDPD void _mm512_i32scatter_pd(void * base, __m256i vdx, __m512d a, int scale);</p>
<p>VSCATTERDPD void _mm512_mask_i32scatter_pd(void * base, __mmask8 k, __m256i vdx, __m512d a, int scale);</p>
<p>VSCATTERDPS void _mm512_i32scatter_ps(void * base, __m512i vdx, __m512 a, int scale);</p>
<p>VSCATTERDPS void _mm512_mask_i32scatter_ps(void * base, __mmask16 k, __m512i vdx, __m512 a, int scale);</p>
<p>VSCATTERQPD void _mm512_i64scatter_pd(void * base, __m512i vdx, __m512d a, int scale);</p>
<p>VSCATTERQPD void _mm512_mask_i64scatter_pd(void * base, __mmask8 k, __m512i vdx, __m512d a, int scale);</p>
<p>VSCATTERQPS void _mm512_i64scatter_ps(void * base, __m512i vdx, __m256 a, int scale);</p>
<p>VSCATTERQPS void _mm512_mask_i64scatter_ps(void * base, __mmask8 k, __m512i vdx, __m256 a, int scale);</p>
<p>VSCATTERDPD void _mm256_i32scatter_pd(void * base, __m128i vdx, __m256d a, int scale);</p>
<p>VSCATTERDPD void _mm256_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m256d a, int scale);</p>
<p>VSCATTERDPS void _mm256_i32scatter_ps(void * base, __m256i vdx, __m256 a, int scale);</p>
<p>VSCATTERDPS void _mm256_mask_i32scatter_ps(void * base, __mmask8 k, __m256i vdx, __m256 a, int scale);</p>
<p>VSCATTERQPD void _mm256_i64scatter_pd(void * base, __m256i vdx, __m256d a, int scale);</p>
<p>VSCATTERQPD void _mm256_mask_i64scatter_pd(void * base, __mmask8 k, __m256i vdx, __m256d a, int scale);</p>
<p>VSCATTERQPS void _mm256_i64scatter_ps(void * base, __m256i vdx, __m128 a, int scale);</p>
<p>VSCATTERQPS void _mm256_mask_i64scatter_ps(void * base, __mmask8 k, __m256i vdx, __m128 a, int scale);</p>
<p>VSCATTERDPD void _mm_i32scatter_pd(void * base, __m128i vdx, __m128d a, int scale);</p>
<p>VSCATTERDPD void _mm_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);</p>
<p>VSCATTERDPS void _mm_i32scatter_ps(void * base, __m128i vdx, __m128 a, int scale);</p>
<p>VSCATTERDPS void _mm_mask_i32scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);</p>
<p>VSCATTERQPD void _mm_i64scatter_pd(void * base, __m128i vdx, __m128d a, int scale);</p>
<p>VSCATTERQPD void _mm_mask_i64scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);</p>
<p>VSCATTERQPS void _mm_i64scatter_ps(void * base, __m128i vdx, __m128 a, int scale);</p>
<p>VSCATTERQPS void _mm_mask_i64scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Overflow, Underflow, Precision, Denormal</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type E12.</p></body></html>